Proceedings of the 1991 International Conference on Parallel Processing, August 12-16, 1991: Architecture

algorithm allocation architecture bandwidth bank barrier binary block broadcast buffer cache coherence cells clock Clos network cluster coherence protocol communication Computer connected crossbar crossbar switch cube cycle dataflow delay destination efficient execution fault fault-tolerant Figure functional units global graph hardware hypercube hypermesh IEEE IEEE Trans implementation input instruction stream interconnection network interleaved iteration latency linear load logic loop machine mapping matrix memory access memory modules memory system MIMD multiple multiprocessor n-cube node number of processors operands operations optimal output overhead packet parallel computer Parallel Processing path perfect shuffle performance permutation pipeline port prefetch problem Proc protocol reconfiguration request routing scalar scheduling scheme shared memory shown signal SIMD simulation stage structure subtree Supercomputing superscalar switch synchronization systolic array task techniques Theorem threads tion token queue topology tree Univ update vector VLIW