Hardware Security: Design, Threats, and SafeguardsCRC Press, 29.10.2014 - 542 Seiten Design for security and meet real-time requirements with this must-have book covering basic theory, hardware design and implementation of cryptographic algorithms, and side channel analysis. Presenting state-of-the-art research and strategies for the design of very large scale integrated circuits and symmetric cryptosystems, the text discusses hardware intellectual property protection, obfuscation and physically unclonable functions, Trojan threats, and algorithmic- and circuit-level countermeasures for attacks based on power, timing, fault, cache, and scan chain analysis. Gain a comprehensive understanding of hardware security from fundamentals to practical applications. |
Inhalt
Part II Hardware Design Of Cryptographic Algorithms | 83 |
Part III Side Channel Analysis | 177 |
Part IV Hardware Intellectual Property Protection | 347 |
Part V Hardware Trojans | 379 |
Part VI Physically Unclonable Functions | 473 |
Bibliography | 505 |
Back Cover | 535 |
Andere Ausgaben - Alle anzeigen
Hardware Security: Design, Threats, and Safeguards Debdeep Mukhopadhyay,Rajat Subhra Chakraborty Eingeschränkte Leseprobe - 2014 |
Hardware Security: Design, Threats, and Safeguards Debdeep Mukhopadhyay,Rajat Subhra Chakraborty Eingeschränkte Leseprobe - 2014 |
Häufige Begriffe und Wortgruppen
adversary analysis approach architecture bitstream block cipher cache attacks CDFG chip circuit clock cycles column composite field computation configuration corresponding countermeasure cryptographic decryption denoted dummy round elements elliptic curve encryption example fault model faulty ciphertexts FIGURE finite field Fmax FPGA function Hamming Distance Hamming Weight hardware Trojans Hence hypotheses IDDT implementation injected input inserted inverse irreducible polynomial Karatsuba algorithm Karatsuba multiplier key bytes Key Schedule logic mapping masked matrix memory access MixColumns modification module multiplication netlist nodes obfuscation observed obtained operation output overhead pattern performed pipeline plaintext polynomial power consumption power traces process variations processor proposed random reduce registers round key S-Box scalar scan chains scheme shown in Fig shows side channel attacks side-channel signal simulation SubBytes techniques transformation trigger Trojan coverage Trojan detection values Xilinx XOR gates