Proceedings of the International Conference on Application Specific Array Processors: September 5-7, 1990, Princeton, New JerseySun Yuan Kung IEEE Computer Society Press, 1990 - 808 Seiten |
Inhalt
ApplicationOriented High Speed Processors Experiences | 1 |
A ProcessorTime Minimal Systolic Array for Transitive Closure | 19 |
Systolic Array Implementation of Nested Loop Programs | 31 |
Urheberrecht | |
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Häufige Begriffe und Wortgruppen
adder algorithm application Array Processors bit-serial block byte CAAPP calculation cell chip circuit clock clustered column communication compensation paths configuration connected coprocessor cycles daughterboard defined delay described domain equations error evaluation example execution fault fault-tolerant FIFO function Gaussian elimination graph hardware HDTV ICAP IEEE implementation input instruction interconnection iteration iWarp linear logic loop Łukasiewicz logic machine mapping matrix memory method MIMD modules multiple neural network neurons node obtained operations optimal output parallel computer partitioning pattern PE's performance pipeline pixel polynomial problem Proc processing elements processor array propagation QR decomposition reconfiguration rotation routing sample schedule scheme shown in Figure Signal Processing SIMD simulated annealing simulation sorting network step structure subrange surrogate file switch systolic array technique transformation unit update variable vector VLSI window